State encoding watermarking for field authentication of sequential circuit intellectual property

This paper proposes a new watermarking scheme for intellectual property (IP) protection of sequential circuits. The method embeds the watermark by encoding the state variables as opposed to modifying the states and edges of state-transition graph (STG) in conventional finite state machine (FSM) watermarking schemes. It has the merits of being applicable to gate-level implementation of sequential circuit without the need to extract the STG; the authorship can be easily authenticated in the field as the watermark is embedded based on testability directed partitioning; and the watermark is hard to be erased by test structure removal and conceivable re-synthesis attacks as it is globally embedded before synthesis and optimization. The scheme has low probability of coincidence and very low logic overhead as evinced by the experimental results on ISCAS benchmark circuits and comparison with the most relevant state-of-the-art IP watermarking scheme.