A novel low gate-count serializer topology with Multiplexer-Flip-Flops

This paper proposes Multiplexer-Flip-Flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose Multiplexer-Latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis shows that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to the traditional pipeline topology. To verify the function of the proposed design, a chips is implemented with the proposed 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the proposed serializer with MUX-FFs are bit-error-free (with BER <; 10
^-12
), operating at up to 12 Gbit/s.