A Side-Channel hardened IP-Protection Scheme for FPGA-based Platforms

At the cutting edge of todays embedded technology FPGA platforms are increasingly utilized for security sensitive applications. Besides the strength of cryptographic IP-cores on FPGAs the reconfiguration process of these modules has to be aware of both, algorithmic and implementation attacks in order to prevent unauthorized usage and counterfeiting. Due to the fact that most resources on the FPGA-based platforms are reserved for computation intensive operations, a lightweight solution for the secure reconfiguration scheme of the protected IP-cores is mandatory. In this work we address these challenges and propose a solution, which combines the research areas of trustworthy reconfiguration and side-channel analysis. The specific contributions to the aforementioned challenges are: (i) Exploration of different PRESENT implementations to optimize the trade-off between throughput and resource utilization. (ii) A side-channel analysis evaluation of different PRESENT implementations. (iii) Integration of an optimized and side-channel aware implementation into an efficient IP-protection scheme on FPGAs.