Spurious effects induced by current switching in power strips of wafer package

Spurious effects due to current switching in power lines on silicon wafer packages (monolithic or hybrid) are analyzed in the time domain. Theoretical results lead to simple relations allowing easy predictions of the dynamic voltage drop on a power line and of the spurious voltages on signal lines induced by crosstalk with power lines. Experimental measurements on typical devices are presented to validate these formulas.<
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