A microelectronic core for a programmable digital hearing aid

We introduce a core for a digital hearing aid that compensates the signal spoken in sensorineural impaired listeners with object of improving their intelligibility. The technique implemented is based on a digital analysis/synthesis of speech: we divided the input signal into short time blocks then we make a multiband analysis, non-linear amplification and synthesis based in a sinusoidal model of the voice, according to the subject's dynamic range in each band. The system works in real time and has been implemented with only one ASIC in 1/spl mu/ ES2 technology including 3 RAM memories with a capacity of 2432 bits and one 16/spl times/16 multiplier. The size of the die is 30.59 mm/sup 2/.