Electrical characterization method to study barrier integrity in 3D through-silicon vias

In this paper, the controlled I-V (IV
_ctrl
) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IV
_ctrl
method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IV
_ctrl
in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.