Threshold voltage and DIBL variability modeling for SRAM and analog MOSFETs

A physically-based variability model is developed to explain threshold voltage (V
_T
) and drain induced barrier lowering (DIBL) variations, and their correlations. Inputs to the model rely on forward (F) and reverse (R) data of measured transistor pair mismatch. Positionally asymmetric and symmetric random dopant fluctuation components of V
_T
and DIBL variability are identified for SRAMs and analog devices from a 32nm HKMG technology and their correlations explained.