Thermal performance of Inkjet-assisted spray cooling in a closed system

As the number of processors per die increase, chip thermal hotspots become increasingly more concentrated within smaller and smaller areas. Furthermore, these hotspots can change as processors are dynamically throttled or taken in and out of sleep mode based upon load and overall thermal budgets. Current cooling solutions (e.g. heatsinks, heatpipes, and even liquid cooling solutions) extract heat from the chip level but cannot independently control temperature at the hotspot level. The presented solution utilizes InkJet heads to deliver precise coolant flow rate independently to each chip location to maintain very high heat transfer rate via sustained liquid-to-vapor phase change. The result is a 10-100x improvement in thermal extraction rates over existing cooling solutions, achieving heat transfer rate as high as 4.5kW/cm². Additionally, because each hotspot is maintained independently eliminating any large temperature gradient over the entire chip surface area, the ability to operate chips at higher operating points is now possible. This paper presents a heat sink prototype based on the inkjet-assisted spray cooling technology. The heat sink utilizes an air-cooled vapor chamber to condense and recirculate the evaporated liquid to achieve a fully closed system within the vapor chamber enclosure. The design of the prototyped solution is presented.

INTRODUCTION

As the number of processor cores per die increase with semiconductor feature size reduction, thermal heat dissipation increases as a limitation on operating performance. Specifically hitting the thermal wall in the past decade has resulted in clock frequencies leveling off as a result of requirements to keep thermal budgets within existing cooling technologies. Further, as features shrink hotspots became more concentrated within even smaller areas and the thermal solutions can no longer simply address dissipation of the thermal average across the chip. Compounding this, multi-cores add two additional challenges: (1) More hotspots distributed broadly across the chip, and (2) greater dynamics in each core's workload. The latter not only includes cores being dynamically placed in sleep mode, but also systems that dynamically boost clock frequency of one core while throttling others to adjust for single thread performance needs.