An efficient lid design for cooling stacked flip-chip 3D packages

3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.