Hot-carrier behaviour and ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology

This work reports the hot-carrier (HC) behavior and specific on-resistance (R
_on,sp
) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×10
⁵
sec stress), and it shows an excellent R
_on,sp
-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and R
_on,sp
= 1.64 mΩ-cm
²
).