Strain relevance on the improvement of the 3T1D cell performance

3T1D-DRAM cell has been stated as a valid alternative to be implemented as a L1 memory cache and substitute 6T-SRAM, highly affected by variability. While scaling down capacitor-less DRAM cells is a challenging trend, in this paper we show how it can be compensated the scaling drawbacks through the channel strain of the cell devices and the proposal of new cell configurations to further enhance the circuit behavior.