Characterization of parameter variability and correlations for FD SOI CMOS technology

A fully-depleted SOI CMOS technology, being implemented in ITE, Warsaw, has been briefly described. Extensive wafer-scale electrical measurements have been done towards investigation of the technology stability. The measurements have been followed by I–V characteristics processing based on compact models of MOS transistors. The calculated electrophysical MOSFET parameters have been mapped and their distributions have been determined. The MOSFET parameter extraction has been supplied with additional measurements of the poly-Si resistors. Correlations between determined parameters have been also investigated.