A radiation hard delta Sigma ADC in 130 nm CMOS

In this paper a radiation tolerant delta Sigma ADC is presented. The design features a 1.5 V, 17 bit Delta Sigma ADC consuming 4.35 mW at a sample frequency of 1 MHz. The ADC features a bandwidth of 1 kHz and utilizes a correlated double sampling technique (CDS) to remove offset and 1/f noise. The circuit maintains its 17 bit resolution upon a simulated radiation dose exceeding 1 MGy and varying temperatures between 0 ºC and 85 ºC. Keywords- Analog integrated circuits, Switched capacitor circuits, CMOS technology, Reactor instrumentation