Development and simulation of PIE encoder architecture for UHF RFID reader based on FPGA

The paper outline development and simulation of Pulse Interval Encoding (PIE) encoder architecture for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader based on Field Programmable Gate Array (FPGA). The PIE encoder architecture presented in this paper is according to International Organization for Standardization and International Electrotechnical Commission (ISO/IEC 18000-6) protocol. The behavior of the PIE encoder architecture is realized by derivation of Verilog Hardware Description Language (HDL) code in Quartus II software. Utilizing the ModelSim-Altera, the PIE encoder architecture is simulated to observe its functionality. The designing of the encoder is intended for uses in UHF RFID passive interrogator.