A moving window architecture for a HW/SW codesign based Canny edge detection for FPGA

This paper proposes an accelerator for Canny edge detection implemented on FPGA. The proposed architecture relies on a moving window consisting of 7×8 pixels, which performs the more computational complex operations of the algorithm: smoothing, gradient's magnitude and direction computation, non-maximum suppression and double thresholding. By employing the proposed window, intermediate results are stored within the FPGA, without the need to buffer them in large memory structures. Furthermore, the design has a high throughput rate, due to its large numbers of pipeline stages, allowing considerable performance for the proposed algorithm.