14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain

To summarize, this paper explores key challenges of FinFET stress engineering that is based on the epitaxial SiGe S/D. These challenges are FinFET-specific and can be addressed by carefully balancing several design and process trade-offs simultaneously. An appropriate 3D modeling methodology is demonstrated to handle the new FinFET-specific design and process challenges.