A logic gate for reversible pipelining

This paper describes a logic gate for reversible pipelining that needs about 2/spl times/(number of input signals) of transistors and 4-phase clock, which is approximately half of those of other circuits either in transistor count or in clock phase. Simulation results of a 2-stage shift register based on this gate show that this implementation with a clock generator dissipates 59% less power than the theoretical power dissipation lower limit of conventional CMOS implementations.