Improvement in radiation-hard CMOS logic gates for noise margin

A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage V/sub DD/.