Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors

Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the proposed mechanism includes four stages: 1) to use parity codes for error detection in the SPM, 2) to keep an address matching table in the main memory to store the address of the copy of SPM blocks in the main memory, in the case of dynamic SPM, 3) to allocate a specific segment of the main memory as an SPM backup, in the case of static SPM, and 4) to recover from errors using an interrupt service routine (ISR). Compared with a single error correction /double error detection (SEC-DED) scheme, by using a 2-bit interleaved-parity per word, the proposed mechanism can correct at least three bit errors, while SEC-DED is capable of correcting only single bit error and detecting 2-bit errors. The experimental results reveal that the energy consumption and area overheads of the proposed mechanism are approximately 22% and 15% less than that of SEC-DED for a 4Kbyte SPM, respectively. Moreover, this mechanism provides 10 times lower performance loss compared with SEC-DED.