Monocrystalline Floating Gate Structure for Ultimate NAND Flash Scaling Towards the 12nm Node

We propose a cell structure with monocrystalline floating gate and 6 nm to 8 nm of thermally grown SiO
₂
interpoly dielectric (IPD) for <;20 nm NAND Flash arrays. This thin IPD avoids the bitline pitch scaling barrier caused by the ONO thickness limitation. Simulations show that, down to the 12 nm node, such cells can be programmed without excessive IPD leakage. The combination of modeling and experimental results indicates that 12nm memory cells with 7 nm SiO
₂
IPD can achieve 10 years data retention.