Abstract:
We have developed a 64Gb MLC NAND Flash using a sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve 800MB/s transfe...Show MoreMetadata
Abstract:
We have developed a 64Gb MLC NAND Flash using a sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve 800MB/s transfer rate, we introduce slim transistors of ~3 nm-thick gate oxide and dual poly gate, in addition to conventional NAND Flash transistors. Furthermore, some new novel circuitry has been implemented, such as Split Power Page Buffer, Local Sense-Amplifier (LSA) Data In/Out Architecture, Regulated Widlar Reference Generator and Low VCC Row Decoder.
Published in: 2012 4th IEEE International Memory Workshop
Date of Conference: 20-23 May 2012
Date Added to IEEE Xplore: 11 June 2012
ISBN Information: