Spacer-Defined EUV Lithography Reducing Variability of 12nm NAND Flash Memories

The NAND Flash memory is the most scaled device nowadays and it is the best candidate to keep pace with the Moore's Law. However, highly scaled memory dimensions decrease to the point where variability effects become the dominating showstoppers. Especially, the Line Edge Roughness (LER) is the dominating key parameter for NAND Flash memory electrical performance, the outcome of novel Lithography processes (Extreme UV patterning multiplication techniques) needed for scaling. This paper addresses these open issues, by presenting the LER-aware model for variability simulation. This paper also proposes the benchmarking considerations and trades-off for different cell architectures (ultimate vs. planar), LER smoothing processes and Error Correcting Codes. In addition, we investigate the variability reduction caused by correlations of LER, produced by Self-Aligned Spacer-Defined on EUV lithography