Investigation of groove surface induced by strain relaxation in selective epitaxy SiGe process

Embedded SiGe or SiGe:B (e-SiGe or e-SiGe:B) PMOS source/drain (S/D) is widely used in advanced CMOS technology. However, with germanium (Ge) content increase, it becomes more and more challenging and critical to control defect and stress relaxation. In the present work, a groove-like surface defect of selective epitaxy SiGe was reported, which can be observed both on blanket wafer and device wafer. The groove-like defect induces very high junction leakage when this e-SiGe process applied in device wafer fabrication. Experimental results show both lattice mismatch and thermal mismatch induce strain relaxation which contributes to this specific surface defect. Two countermeasures were applied to fix these mismatch as well as surface defect, i.e. inserting a buffer layer of Si
_1-x
Ge
_x
or reducing the temperature difference among the different stack layers.