Junction vs. junctionless vertical MOSFET by using partial SOI structure: A 2D simulation study

In this paper, we focus on the electrical characteristics of the partially insulating oxide (PiOX) junctionless vertical MOSFET (JLVFET) and PiOX junction vertical MOSFET (JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, in whereas the PiOX JVFET needs an S/D implant. But, according to simulation results, we find out that the PiOX JVFET exhibits desired characteristics which are similar to those of the PiOX JLVFET. This means that the subthreshold swing and drain-induced barrier lowering, can be almost the same for both devices. Additionally, the high S/D doping presented in the PiOX JVFET helps reduce the parasitic S/D resistance, resulting in an enhanced current drive. In other words, it is believed that the PiOX JVFET is still considered as a candidate for future CMOS scaling.