A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques

This paper presents a digitally-assisted two-step linearity enhancement technique for a 14-bit current-steering digital-to-analog converter. The static nonlinearity introduced by the wittingly small current sources for the sake of area reduction is firstly calibrated by evaluating and compensating the offset current between the average of 6-bit MSB array and the sum of 8-bit LSB array. An unique dynamic element matching (DEM) algorithm is then applied to suppress the residual nonlinearities without introducing too many transient glitches at the output. A 14-bit 200MS/s DAC is fabricated to verify the proposed scheme and successfully demonstrates a decent linearity of 82.5dB SFDR within an area of 0.45mm
²
in a 0.18-µm CMOS process. A good power efficiency is kept at the same time as well.