Synthesis of low-power asynchronous circuits in a specified environment

We introduce a new method for the synthesis of power-optimal asynchronous control-circuits. The method includes two steps: (i) an exact algorithm for 2-level synthesis, and (ii) heuristic algorithms for multi-level synthesis. Unlike most existing synchronous algorithms, we incorporate both temporal dependence and glitch activity in our model to guide synthesis. Results, using only our 2-level minimization, show power reduction up to 33%.