An efficient packing algorithm based on constraint satisfaction problem technique

In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference circuits from the given user logic circuit using specific constraints. Due to complex architecture of FPGA, to enumerate all the reference circuits in a fine-grain manner is impractical. Consequently, coarse-grain manner is adapted in the paper to overcome this problem. The experimental results show that the proposed algorithm achieves comparable performance in area and speed compared with literatures.