Challenges of III–V materials in advanced CMOS logic

The superior transport properties of III–V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III–V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<10nm, N
D
=5×10
¹⁹
cm
⁻³
, ρ
c
= 6Ω.µm
²
and Dit = 4×10
¹²
eV
⁻¹
cm
⁻²
. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.