An efficient FFT/IFFT architecture for wireless communication

In recent times, DSP algorithms have received increased attention due to rapid advancements in multimedia computing and high-speed wired and wireless communications. For the portability requirement in telecommunication systems, there is a need for low power hardware implementation of Fast Fourier Transforms algorithm. The FFT processor is the most computationally intensive component in OFDM communication, the power efficiency improvement of this component can have great impacts on the overall system.. In this paper, we present an efficient implementation of a reconfigurable FFT/IFFT processor for wireless applications. Our design adopts a single-path delay feedback style as to eliminate the read-only memories (ROM's) which is used to store the twiddle factors. Elimination of ROM done by applying the proposed reconfigurable complex constant multiplier and bit-parallel multipliers, thus consuming lower power than the existing works.