Asynchronous sub-logarithmic adders

Fast arithmetic operators have always been an important topic in computer design. There are two kinds of arithmetic operators: fixed-time and variable-time ones. While fixed-time arithmetic operators have been widely studied, variable-time operators seem to be more and more interesting for low-power design and very high performance computing. Self-timed arithmetic operators are able to deliver their result in an average computation time less than the worst case time. We present an architecture, which is a variant of the carry select adder, for the addition of n-bit numbers with a O(/spl radic/(log/sub 2/n)) average computation time.