Implementation of sorting algorithms in reconfigurable hardware

The paper discusses data sorting algorithms which create and traverse tree-like data structures and permit fast resorting. Optimization is achieved through rational grouping of previously developed methods allowing address-based representation and compact coding of data items. The results of hardware implementation of the algorithms and prototyping in FPGA (Field-Programmable Gate Arrays) demonstrate that: 1) sorting algorithms can be implemented efficiently in low-cost FPGA; 2) the developed coding technique permits data items to be compactly represented in memory; 3) combining different sorting methods produces the best results in terms of performance and memory requirements; 4) low-cost devices can only be used to tackle limited sets of data (up to 2²⁰ in a Spartan-3 1200 FPGA) and for processing more data either a more powerful FPGA or an external memory is required.