A Parallel Adaptive Range Coding Compressor: Algorithm, FPGA Prototype, Evaluation

Loss less compression algorithms are employed in a wide variety of communication- and storage-related systems. Many embedded applications, such as real-time communication log compression used in automotive systems, impose strict throughput constraints on the compression unit, creating a demand for hardware-accelerated designs. In this paper we present a modification of the Adaptive Range Coding algorithm used by 7-Zip compressor implemented in an Field Programmable Gate Array (FPGA). We have improved the algorithm to support massive parallelization that allows making use of the distributed FPGA logic and achieving compression throughput of more than 50MB/s when implemented on a Virtex5 FPGA in conjunction with a hardware LZSS coder. Compared to a fixed-table Huffman encoder, our implementation provides the same high throughput and a 20% better compression ratio. Furthermore we explore several variations of algorithm parameters and show various trade-offs between compression efficiency, FPGA utilization and throughput.