Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing

Discrete Gate Sizing is a commonly used technique for power and/or timing optimization. The accuracy of delay and power models play an important role during the optimization process, since circuit delay and power must be estimated in each gate change step to check its feasibility. Although accurate delay and power models are desirable to achieve good optimization results, they are non-convex and that is why most of gate sizing techniques found in the literature adopt simplified models. In addition, accurate models may lead to prohibitively long execution times. In this paper we evaluate the use of five different strategies to propagate the impact of slew impact on delay and power of circuit gates in discrete gate sizing. These strategies differ one from each other by the number of considered logic levels updated, with respect to the changed gate. Experimental results showed that the strategy that considers the impact of a gate change on its fan-ins and three levels of fan-out gives better delay and power estimates leading to an excellent trade-off between power reduction and execution time. In addition, such strategy also prevents timing violations from being overlooked.