Hybrid Memristor-CMOS memory cell: Modeling and design

Memristor was realized as physical device recently by HP labs, this discovery spurred a great interest in memristors as a fundamental electronic element. Memristor-based technology provides much better scalability, higher utilization when used as memory, and overall lower energy consumptions compared to traditional CMOS technology. The contribution of this paper is a detailed study of the non-linear model of the Memristor. This modeling is used to recognize the time and the voltage characteristics of stable read and write operations, and the tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area. Based on this modeling we propose a hybrid CMOS-Memristor memory cell and architecture that deliver the speed of an SRAM and the density of DRAM with no wasted leakage power in the storage.