A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI

Near-threshold computing exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-V
_DD
operation: degraded logic delay resulting in significantly lower throughput than at super-threshold, and excessive, unpredictable delay variation caused by increased sensitivity to process and dynamic variations.