LVDS I/O buffers with a controlled reference circuit

A controlled reference circuit maintains the output voltage levels and current values of an LVDS output buffer constant over (PVT) processing, voltage supply, and temperature variations. The reference circuit requires one external resistor and generates two DC control voltages which are applied to all output buffers. An on-chip resistance is described which maintains a tightly controlled impedance of approximately 100 /spl Omega/ over the common mode range of 0 to 2.4 V. A measured waveform at 1.244 Gb/s is given.