Low-voltage multi-level flash memory: determination of minimum spacing between multi-levels [CMOS]

This paper reports that cell reliability issues (e.g. V/sub T/ spread, program disturb, read disturb, subthreshold leakage current, and charge retention), read scheme, and cell structures are the factors for minimizing V/sub T/ spacing for multi-level storage in flash memory. A 2T cell structure is proposed for wider V/sub T/ window, high speed read, and smaller V/sub T/ spacing in order to store more V/sub T/ levels than 1T cell.