A 4GS/s 3b two-way time-interleaved ADC in 0.13um CMOS

A time-interleaved ADC,2 channels each consisting of a track-and-hold circuit with self-biased buffer and a 2GS/s flash ADC,is presented. The sub-ADC is composed of one-stage pre-amplifiers, latches and standard digital encoders with TSPC D-flip-flops. A half-reset latch is proposed to operate at sampling rate of 2GS/s with improved power consumption. 2.91b ENOB and 25.46dB SFDR are gotten by simulation at Nyquist frequency. The FoM of the ADC including T/H is 1.51 pJ/conv.-step.