Area efficient LDPC decoder design for parallel layered decoding

An area efficient LDPC decoder hardware design for parallel layered decoding algorithm is proposed. Shift register chain is used to reduce the chip area. Puncturing technique is employed to produce arbitrary rate between 1/2 and 1. This design is implemented based on rate-1/2 LDPC in 802.16e with 65nm CMOS. The decoder achieves a throughput of 1.2 Gb/s at 10 iterations with an area of 1.14mm² and support any rate between 1/2 and 1.