Design and implementation of SIMD Vector Processor on FPGA

This paper handle the design and implementation of the SIMD Vector Processor on FPGA, this processor consist of 4 parallel lanes (processing elements PEs) that work simultaneously independent with each other, each one of those lanes has its own arithmetic units, vector register file which represents a part of the main distributed register file also it has a local memory for storage of execution results of that lane, lanes's local memories connects to each other to exchange their contains via interconnection networking that can be configure software to give a certain topology of static interconnection network, like (Mesh, Star,...etc) those lanes and their memories act a vector part of the SIMD Vector Processor. A scalar processor also designed and attached with the vector part in order to accomplish scalar instructions that can not be handle by vector lanes, this processor also has its scalar register file and set of arithmetic units.