Realtime regular expressions for analog and mixed-signal assertions

Syntax and semantics are proposed for realtime (i.e., continuous-time) regular expressions, which extend and generalize existing SVA regular expressions. The extensions are motivated by practical needs for AMS circuit verification and were developed as part of the authors' contribution to analog assertions work in the Accellera committee standardizing Verilog-AMS. Given a suitable notion of sampling, we prove that the realtime semantics provided for the existing SVA clocked digital regular expressions is equivalent to the original discrete semantics. As a result, the existing digital operators can intermix freely with the new realtime operators, which is a major contribution of our framework. We also investigate the theoretical relationship between our framework and the timed regular expressions of Asarin, Caspi, and Maler. We provide a semantically faithful embedding of timed regular expressions into our realtime regular expressions, as well as a construction of timed automata recognizers for our realtime regular expressions. These constructions show that our realtime regular expressions are no less expressive than the timed regular expressions of [1] and no more expressive than the generalized timed regular expressions of [2]. The automata recognizers also provide the basis for an implementation strategy for our framework.