FPGA implementation of high speed XTS-AES for data storage devices | IEEE Conference Publication | IEEE Xplore

FPGA implementation of high speed XTS-AES for data storage devices


Abstract:

This paper presents a novel architecture of XTS-AES mode for data storage devices. An enhanced fully pipelined and area efficient XTS-AES mode design using one AES core i...Show More

Abstract:

This paper presents a novel architecture of XTS-AES mode for data storage devices. An enhanced fully pipelined and area efficient XTS-AES mode design using one AES core is proposed. We propose a design of XTS module to handle the data blocks to be encrypted using a single AES core. Considering previous work in XTS, few designs have been published that use a single AES core, and few efforts have been targeted toward their optimization. This paper describes hardware implementation of XTS-AES design with a throughput of 19.56 Gbps and a maximum achievable frequency of 153.84 MHz. This design is written in Verilog HDL and verified on Altera Cyclone II FPGA.
Date of Conference: 11-14 December 2011
Date Added to IEEE Xplore: 09 February 2012
ISBN Information:
Conference Location: Abu Dhabi, United Arab Emirates

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