Power-efficient multiplier-accumulator design for FIR filters

Several low-power design techniques have been applied to the design of a power efficient multiplier-accumulator (MAC) array. The addition operation has been interleaved into the multiplier array. The MAC array is designed to have a programmable resolution so that the blocks corresponding to the least significant bits can be deactivated when a lower resolution is sufficient. The multiplier-accumulator has been designed in a 3.3 Volt 0.5 /spl mu/m CMOS technology.