Small: A programming language for state machine design

A small and simple language for sequential design is introduced. Synchronous state-machine design is often expressed using graphical notations such as Algorithmic State Machine (ASM) charts and state transition diagrams. An alternative is to use common hardware description languages such as VHDL or Verilog. For both teaching and design purposes, neither approach is satisfactory. ASM charts and similar notations invite unstructured designs and allow parallelism only at the outermost level. Educational implementations appear not to exist. VHDL and Verilog are geared toward asynchronous behaviour - in expressing synchronous designs the clock signals must be made explicit. Also they are large, complex languages with complex semantic foundations. SMALL (State Machine Algol-Like Language) is a small and simple imperative programming language, designed specifically for hardware implementation. It bears roughly the same relationship to ASM charts as Algol-like software languages bear to flowcharts.