Low power design and dynamic power management system for VLIW DSP subsystem

In this paper, we introduce the VLIW DSP subsystem for multi-core software development and SoC prototyping. The DSP subsystem consists two DSP cores (65nm PACDSP V3F) and a FPGA chipset (Virtex5 XC5VLX330), which is a multi-core solution. The flexibility of FPGA makes it easier to integrate two DSP cores into different platforms, and system integrators can accord to their requirement to use different off-chip memory subsystem by implement different memory controller. For high-performance DSP core, thermal issues and power consumption are becoming major design constraints. Temperature variations are adversely affecting the chip reliability. In order to reduce both thermal effects and power dissipations, we develop twelve thermal sensors and several low power design techniques in the DSP subsystem, such as dynamic power management system and thermal-aware configurable instruction memory subsystem. In the DSP subsystem, an energy-effective cell-based design has been produced by analyzing the relationships between the energy efficiency and the synthesis constraints. The DSP core is fabricated in the TSMC 65nm CMOS technology. The estimated power dissipations can save about 12%~18% by using thermal-aware configurable instruction memory subsystem in H.264 decoder, JPEG decoder and AAC decoder.