Doppler optimized iterative reweighed lest square mismatch pulse compression algorithm realization on the FPGA

This paper presents an approach for the mismatch pulse compression implementation in spread spectrum radars with binary phase intra-pulse modulated pulses. Design and verification of the matched and mismatched filter for signals coded by Barker and M sequences are accomplished on a digital radar signal synthesis and processing platform based on direct digital synthesis (DDS) and field programmable gates array (FPGA) technology. Coefficients of mismatched filters are obtained by DIRLS algorithm with 16-bit resolution. The compressors are verified with sequences lengths of 13 and 31, and bandwidth of 3.3 MHz.