Low power synchronous buffer based Queue for 3D MPSoC

The buffer plays an important role in the design of MPSoC. The buffer mechanism influences the efficiency of link bandwidth. The buffer also provides a mechanism to synchronize the speed between the routers. The buffers are used to store packets or flits when they cannot be forwarded right away onto the output port. The paper presents discussion on buffering techniques used in the design of MPSoC. We have designed a synchronous Queue for 3-D MPSoC which could perform read and write operation at the same time. Firstly, we have designed a buffer using a multiplexer and a flip flop, and then we have proposed a buffer which would save at least 25% area of what we are using for mux based memory. It is designed using AND gated clock which also saves more power than any other design. We have generated full and AlmostFull signal to avoid overflow. The AlmostFull signal will be HIGH when only one location is EMPTY to write data. The AlmostFull and Full signals eliminate the overhead of sending credit information at every cycle. Thus, power dissipation from the buffers is reduced. The designed buffer using multiplexer operates at the maximum frequency of 755MHz and the proposed buffer has achieved a maximum frequency of 875 MHz on Vertex 6 device.