CMOS Voltage Divider based Current Mirror

This work proposes the Novel design of a CMOS Voltage Divider based Current Mirror that is suitable for Low current biasing applications. The input/output characteristics of the proposed current mirror are discussed. Designed circuit is simulated in a proprietary 180 nm CMOS process, using Cadence Spectre and UMC models. Based on simulation and test results of the newly proposed design, the minimal power consumption is being highlighted. When compared with Basic Current Mirror circuits, CMOS Voltage Divider based current mirror achieves 75% of saving in power consumption.