A tunneling field-effect transistor using side metal gate/high-k material for low power application

Supply voltage (V
_DD
) scaling has been an important issue as the CMOS scaling down. Scaling of devices induces large leakage current due to Short Channel Effects (SCEs). Also, Subthrehold Swing (SS) value of CMOS devices is theoretically limited to 60 mV/dec. Various structures have been proposed to overcome power dissipation problems, one of which is the TFETs [1-2]. However, TFET has two critical drawbacks such as low on-current level and ambipolar behaviors. To overcome these disadvantages, TFET using hetero-gate dielectric materials has been lately reported [3]. Although this TFET has low SS and high on-current level, it is difficult to control dielectric alignment between high-k material and SiO
₂
in the process. Thus, we introduce an improved TFET in terms of fabrication and performance.