Physical design exploration of 3DIC wireless transceiver using through-si-vias

3DIC's, the flagship for the “More than Moore Law” movement are already an integral part of the Semiconductor and Manufacturing industry and lot of investigations are going on within different sectors of the industry to efficiently fabricate 3DIC's. If you peep deep into the design process, everyone is trying to make it upward compatible with the 2D design for effective reusability. The methodology to design and verify the 3DIC involves a collaboration of different people from EDA, CAD, Physical design, Fabrication, TSV and Modeling departments. Different aspects need to be considered for the 3DIC apart from the miniaturization and the resulting space, cost & signal loss savings. The considerations include Power & clock Distribution, Thermal analysis, EMI, ESD protection scheme etc. This paper focuses on the physical design process steps carried out to develop a 3DIC Wireless Transceiver and it throws light into some of the process intricacies which are faced while carrying out the design and verification of such an IC stacking.